Leong and Jabri : a Low Power Vlsi Arrhythmia Classifier 3
نویسندگان
چکیده
The design, implementation and operation of a low power multilayer perceptron chip (Kakadu) in the framework of a cardiac arrhythmia classiication system is presented in this paper. This system, called MATIC, makes timing decisions using a decision tree, and a neural network is used to identify heartbeats with abnormal morphologies. This classiier was designed to be suitable for use in implantable devices and a VLSI neural network chip (Kakadu) was designed so that the computationally expensive neural network algorithm can be implemented with low power consumption. Kakadu implements a (10,6,4) perceptron and has a typical power consumption of tens of microwatts. When used with the arrhythmia classiication system, the chip can operate with an average power consumption of less than 25nW.
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